/*
*	This is the first level cache
*	Use Write-Back
*	Use fully-associative
*/

`include"definitions.v"
module CacheFst(
	//IO from and to CPU
	//Data trans
	PCIn,	
	ALUIn,
	WriteData,
	Writable,
	DataOut,
	InstrOut,
	//Control trans
	CPUReadData,		//CPU tell me it wants a data
	CPUDataReady,		//tell CPU Data has fetched
	CPUInstrReady,		//tell CPU Instr has fetched
	
	//IO from and to CacheSnd
	AskTag,				//CacheFst ask for the block with AskTag 
	AskDataReady,		//CacheSnd show the block we asked for is OK
	CacheL2Data,		//The block CacheL2 fetched for me
	WriteBackable,		//A Write instruction need to Writeback
	WriteBackData		//The Write Back Data
);
//IO declarations
input[31:0] PCIn, ALUIn,WriteData;
input Writable,CPUReadData;
output[31:0] DataOut,InstrOut;
output CPUDataReady,CPUInstrReady;
reg[31:0] DataOut,InstrOut;

input AskDataReady;
output WriteBackable



// Construction of CacheFst
reg valid[31:0],dirty[31:0];
reg[21:0] tag[31:0];
reg[255:0] block[31:0];

wire[21:0] PCtag,ALUtag;
wire[4:0] PCblock,ALUblock;
wire[2:0] PCword,ALUword;

assign PCtag = PCIn[31:10];
assign PCblock = PCIn[9:5];
assign PCword = PCIn[4:2];
assign ALUtag = ALUIn[31:0];
assign ALUblock = ALUIn[9:5];
assign ALUword = ALUIn[4:2];

always @(PCIn) begin
	//TODO
end

always @(ALUIn or CPUReadData) begin
	//TODO

end

always @(WriteData or Writable) begin

end
	//TODO

endmodule
